Method for fabricating semiconductor component with adjustment circuit for adjusting physical or electrical characteristics of substrate conductors

ABSTRACT

A semiconductor component includes adjustment circuitry configured to adjust selected physical and electrical characteristics of the component or elements thereof, and an input/output configuration of the component. The component includes a semiconductor die, a substrate attached to the die, and terminal contacts on the substrate. The adjustment circuitry includes conductors and programmable links, such as fuses or anti-fuses, in electrical communication with the die and the terminal contacts. The adjustment circuit can also include capacitors and inductance conductors. The programmable links can be placed in a selected state (e.g., short or open) using a laser or programming signals. A method for fabricating the component includes the steps of forming the adjustment circuitry, and then placing the programmable links in the selected state to achieve the selected adjustment.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a division of Ser. No. 11/210,562, filed Aug. 24,2005, which is a division of Ser. No. 10/403,741, filed Mar. 31, 2003,U.S. Pat. No. 7,007,375, which is a division of Ser. No. 10/140,340,filed May 6, 2002, U.S. Pat. No. 6,753,482.

This application is related to Ser. No. 10/745,040, filed Dec. 22, 2003,U.S. Pat. No. 6,914,275.

FIELD OF THE INVENTION

This invention relates generally to semiconductor manufacture, and moreparticularly to an improved semiconductor component having adjustablecharacteristics and configurations. This invention also relates to amethod for fabricating the component, and to systems incorporating thecomponent.

BACKGROUND OF THE INVENTION

Semiconductor components, such as chip scale packages, ball grid array(BGA) devices, flip chip devices, and bare dice include terminalcontacts, such as contact balls, contact bumps or contact pins. Theterminal contacts provide the input/output configuration for acomponent, and permit the component to be surface mounted to asupporting substrate, such as a printed circuit board (PCB).Semiconductor components also include semiconductor dice, and theterminal contacts can be formed on substrates attached to the dice, orin some cases formed directly on the dice. For some components, such aschip scale packages, BGA devices, and bumped dice, the terminal contactscan be arranged in a dense grid array, such as a ball grid array (BGA),or a fine ball grid array (FBGA).

The terminal contacts are in electrical communication with integratedcircuits, and other electrical elements, contained on the dice.Typically the components include patterns of conductors that provideseparate electrical paths between the terminal contacts and theintegrated circuits. The conductors can comprise metal traces formed onsubstrates attached to the dice, or formed directly on the dice. Thephysical and electrical characteristics of these conductors can affectthe performance of the component, and the integrity of the signalstransmitted through the terminal contacts to or from the integratedcircuits on the component. For example, plating buses are routinely usedto electrically connect all of the conductors on a component during thefabrication process. The plating buses facilitate plating of bondingpads for the terminal contacts, and wire bonding pads for wire bondingthe conductors to the dice. Following the plating process, the platingbuses are trimmed, such that the conductors are no longer electricallyconnected to one another. However, portions of the plating buses canremain on some of the conductors following the trimming process. Theseremnant portions of the plating buses add mass and length to theconductors, which can affect electrical characteristics, such asinductance, capacitance and resistance. Other physical characteristicssuch as overall lengths, location on the component and proximity toother elements can also affect the electrical characteristics of theconductors.

The terminal contacts associated with the conductors will also havedifferent electrical characteristics, and the characteristics of thesignals transmitted through the terminal contacts will be different.These signal variations can adversely affect the operation of theintegrated circuits on the components, particularly at high clockingspeeds (e.g., 500 MHz or greater). It would be desirable to have thecapability to adjust the electrical characteristics of the conductorsand terminal contacts for semiconductor components, and of otherelements of the components as well.

It would be also be advantageous to be able to adjust the electricalconfiguration of the components as well. For example, it may benecessary to electrically connect or disconnect different terminalcontacts on a component to alter the input/output configuration of thecomponent. This may be necessary because standardized components areoften fabricated with different types of dice. As such, theconfiguration of the terminal contacts for a component containing a diewith a X4 pin assignment configuration may be different than theconfiguration required for the same component having a die with a X16pin assignment configuration. In the prior art different input/outputconfigurations have been achieved by using different layouts for theterminal contacts and the conductors, or by using different wire bondingarrangements between the dice and the conductors.

Also in the prior art, fuses have been used for isolating defectivecircuitry and for substituting redundant circuitry on a component. Forexample, a 16 megabit DRAM memory die may have a small percentage ofcells that fail following burn-in testing. Fuses can be used to isolatedefective integrated circuitry, and to substitute redundant integratedcircuitry. Fuses can be controlled using electrical signals, or by usinga laser beam directed at a portion of the fuse.

Fuses have also been used in the art to lock in operating clockmultipliers for microprocessor components. This type of microprocessoris manufactured by Advanced Micro Devices, Inc. of Sunnyvale, Calif.,under the trademark “ATHLON”.

The present invention provides a method for adjusting thecharacteristics of semiconductor components and elements thereof, andfor customizing the input/output and electrical configuration ofsemiconductor components as well.

SUMMARY OF THE INVENTION

In accordance with the present invention, an adjustable semiconductorcomponent, a method for fabricating the component, and electronicassemblies incorporating the component, are provided.

The component includes a substrate, a semiconductor die attached to thesubstrate, and terminal contacts on the substrate in electricalcommunication with the die. The component also includes adjustmentcircuitry on the substrate configured to adjust physical or electricalcharacteristics of the component or elements thereof.

The adjustment circuitry includes conductors in electrical communicationwith the integrated circuits on the die and with the terminal contacts.The adjustment circuitry also includes programmable links, such as fusesor anti-fuses, in electrical communication with the conductors. Theprogrammable links are configured for placement into different states(e.g., short or open) using lasers or electronic signals.

Depending on the layout of the conductors and programmable links,different physical or electrical characteristics can be adjusted by theadjustment circuitry. For example, the adjustment circuitry can beconfigured to trim the conductors, such as to trim portions of platingbuses associated with the conductors. In addition, the adjustmentcircuitry can include capacitors for adding capacitance to theconductors. Further, the adjustment circuitry can include conductiveloops for adding inductance to the conductors.

The adjustment circuitry can also be used to change the input/outputconfiguration of the terminal contacts, and thus the electricalconfiguration of the component. In this regard, standard substrates canbe wired to different types of dice using a standardized wire bondingarrangement. The electrical paths to the terminal contacts can then beconnected or disconnected using the conductors and the programmablelinks to achieve a desired input/output configuration. For example,memory dice can be wire bonded to the conductors at the widestconfiguration possible (e.g., sixteen DQs (X16)). For a die having asixteen DQs configuration (X16), no changes to the conductors arerequired. For a die having a four DQs configuration (X4), theprogrammable links can be configured to remove all of the conductorsassociated with the unused 12 DQs.

A method for fabricating the adjustable component can be performed on astrip, such as an organic leadframe, containing multiple substrates,which can be singulated into individual components. The method includesthe step of forming the adjustment circuitry on the substrates byforming the conductors and the programmable links in a required layout.Depending on layout and elements, the adjustment circuitry can beconfigured to adjust different physical and electrical characteristicsof the conductors, or the input/output configuration of the terminalcontacts. The method also includes the step of placing the programmablelinks in a selected state (e.g., short or open) to connect or disconnectthe conductors, and to achieve the desired adjustment. Depending on thetype of programmable link, the placing step can be performed using alaser or electronic signals.

The component can be used to construct systems such as MCM packages,multi chip modules and circuit boards.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an enlarged schematic side elevation view illustrating asemiconductor component constructed in accordance with the inventionwith adjustable electrical characteristics;

FIG. 2 is an enlarged cross sectional view of the component, taken alongline 2-2 of FIG. 1;

FIG. 3 is a partial, enlarged cross sectional view, taken along line 3-3of FIG. 2, illustrating adjustment circuitry on the component;

FIG. 3A is an enlarged cross sectional view, taken along line 3A-3A ofFIG. 3, illustrating a substrate and solder mask of the component;

FIG. 3B is an enlarged cross sectional view, taken along line 3B-3B ofFIG. 3, illustrating a conductor of the component;

FIG. 3C is an enlarged cross sectional view, taken along line 3C-3C ofFIG. 3, illustrating a wire bonding pad of the component;

FIG. 3D is an enlarged cross sectional view, taken along line 3D-3D ofFIG. 3, illustrating a bonding pad for a terminal contact of thecomponent;

FIG. 3E is an enlarged cross sectional view, taken along line 3E-3E ofFIG. 3, illustrating a programmable link of the component;

FIG. 4 is an enlarged cross sectional view equivalent to FIG. 3illustrating adjustment circuitry on an alternate embodiment componenthaving adjustable capacitance characteristics;

FIG. 5 is an enlarged cross sectional view equivalent to FIG. 3illustrating adjustment circuitry on an alternate embodiment componenthaving adjustable inductance characteristics;

FIGS. 6A-6F are schematic cross sectional views illustrating steps in amethod for fabricating the semiconductor component;

FIG. 7A is a view taken along line 7A-7A of FIG. 6A illustrating aleadframe used in the method;

FIG. 7B is a view taken along line 7B-7B of FIG. 6B illustratingadjustment circuitry on the component of FIG. 4;

FIG. 7C is a view equivalent to FIG. 7B illustrating adjustmentcircuitry on the component of FIG. 4;

FIG. 7D is a view taken along line 7D-7D of FIG. 6B illustratingadjustment circuitry on the component of FIG. 5;

FIGS. 8A and 8B are schematic cross sectional views equivalent to FIGS.6B and 6C respectively, illustrating an alternate embodiment of thefabrication method wherein electronic signals are utilized to programcurrent-type programmable links;

FIG. 9A is a schematic plan view of a programmable link in the form of acurrent fuse configured for use with the fabrication method of FIGS. 8Aand 8B;

FIG. 9B is a schematic cross sectional view of a programmable link inthe form of an anti-fuse configured for use with the fabrication methodof FIGS. 8A and 8B;

FIG. 10A is a schematic plan view of a multi chip module systemconstructed using components constructed in accordance with theinvention; and

FIG. 10B is a schematic cross sectional view of a system in a packageconstructed using components constructed in accordance with theinvention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIGS. 1 and 2, a semiconductor component 10 constructed inaccordance with the invention is illustrated. As used herein, the term“semiconductor component” refers to an element, or to an assembly, thatincludes a semiconductor die. In the illustrative embodiment, thecomponent 10 comprises a board-on-chip (BOC) semiconductor package.However, the semiconductor component 10 can comprise another type ofsemiconductor package such as a chip-on-board (COB) package, a chipscale package (CSP), a BGA device, a flip chip device, or a bumpedsemiconductor die.

The component 10 includes a substrate 12 having a first surface 14 (FIG.2), and an opposing second surface 16 (FIG. 2). The first surface 14,and the second surface 16, are the major planar surfaces of thesubstrate 12. The substrate 12 also includes a wire bonding opening 18therethrough, extending from the first surface 14 to the second surface16.

In addition, the substrate 12 includes adjustment circuitry 19 (FIG. 2)formed on the first surface 14 of the substrate 12, and a die attacharea 22 formed on the second surface 16 of the substrate 12. Theadjustment circuitry 19 includes a pattern of conductors 20 (FIG. 2),and programmable links 50A, 50B (FIG. 3) in electrical communicationwith the conductors 20.

The conductors 20 can comprise a highly conductive metal which isblanket deposited on the substrate 12, and then etched in requiredpatterns. Alternately, an additive process, such as electrolessdeposition through a mask, can be used. Suitable metals for theconductors 20 include copper, aluminum, titanium, tungsten, tantalum,platinum, molybdenum, cobalt, nickel, gold, and iridium.

The substrate 12 can comprise an electrically insulating material, suchas an organic polymer resin reinforced with glass fibers. Suitablematerials for the substrate 12 include bismaleimide-triazine (BT), epoxyresins (e.g., “FR-4” and “FR-5”), and polyimide resins. These materialscan be formed with a desired thickness, and then punched, machined, orotherwise formed with a required peripheral configuration, and withrequired features. A representative thickness of the substrate 12 can befrom about 0.2 mm to 1.6 mm.

The substrate 12 also includes a solder mask 24 on the first surface 14,and a solder mask 26 on the second surface 16. The solder masks 24, 26can comprise a photoimageable dielectric material, such as a negative orpositive tone resist.

As shown in FIG. 2, the component 10 includes an array of terminalcontacts 28 on the substrate 12 in electrical communication withintegrated circuits, or other electrical elements contained on thecomponent 10. The terminal contacts 28 provide separate electricalconnection points for transmitting (writing) and receiving (reading)electronic signals from the component 10. In addition, the terminalcontacts 28 provide a structure for bonding the component 10 to asupporting substrate, such as a printed circuit board or modulesubstrate.

In the illustrative embodiment, the terminal contacts 28 comprisegenerally spherically shaped contact balls in a ball grid array (BGA),or a fine ball grid array (FBGA). However, the terminal contacts 28 cancomprise other conventional contacts having other shapes, and arrangedin other patterns, to provide multiple electrical connection points forthe component. By way of example, representative contacts include bumps,columns, studs, domes, cones, pins and pads. Also, the terminal contacts28 can be made of any electrically conductive material, such as a solderalloy, copper, nickel, or a conductive polymer.

As shown in FIG. 1, the terminal contacts 28 have a diameter “D” and aspacing or pitch “P”. With the terminal contacts 28 comprising contactballs in a ball grid array, or a fine ball grid array, a representativerange for the diameter D can be from about 0.127 mm (0.005 inch) to0.762 mm (0.030 inch). A representative range for the pitch P can befrom about 0.228 mm (0.008 inch) to 2.0 mm (0.078 inch).

As shown in FIG. 2, the component 10 also includes a semiconductor die30, and a die encapsulant 42 on the die 30 and on the second surface 16of the substrate 12. The die 30 can comprise a conventionalsemiconductor die having a desired configuration. For example, the die30 can comprise a dynamic random access memory (DRAM), a static randomaccess memory (SRAM), a flash memory, a microprocessor, a digital signalprocessor (DSP), or an application specific integrated circuit (ASIC).

The die 30 includes a row of bond pads 32 formed on a face portionthereof, in electrical communication with the integrated circuitscontained on the die 30. The die 30 is bonded face down to the dieattach area 22 of the substrate 12, with the bond pads 32 on the die 30aligned with the bonding opening 18 in the substrate 12.

As shown in FIG. 2, an adhesive layer 34 bonds the die 30 to the dieattach area 22 on the substrate 12. The adhesive layer 34 can comprise afilled epoxy, an unfilled epoxy, an acrylic, a polyimide or an adhesivetape material. In addition, wires 36 are placed through the wire bondingopening 18 in the substrate 12, and are wire bonded to the bond pads 32on the die 30, and to corresponding wire bonding pads 40 on thesubstrate 12. A wire bond encapsulant 38 fills the wire bonding opening18 and encapsulates the wires 36. The wire bond encapsulant 38 cancomprise a polymer material, such as a glob top of epoxy or silicone,deposited in a desired shape using a suitable process such as dispensingthrough a nozzle, and then cured as required.

Referring to FIG. 3, the adjustment circuitry 19 also includes terminalcontact bonding pads 44 on the substrate 12 configured to providebonding sites for bonding the terminal contacts 28 to the substrate 12.The terminal contact bonding pads 44 are in electrical communicationwith the conductors 20 and with the wire bonding pads 40. In addition,the terminal contact bonding pads 44 are in electrical communicationwith plating conductors 20P on the substrate 12 that extend to an edge54 of the substrate 12. As will be further explained, the platingconductors 20P are initially connected to plating buses, which are usedto apply a current to the terminal contact bonding pads 44, and to thewire bonding pads 40, for plating non-oxidizing metal layers 46 (FIGS.3C and 3D) such as gold or platinum layers. These non-oxidizing metallayers 46 facilitate the bonding process for the terminal contacts 28and the wire bonding process to the die 30.

As shown in FIGS. 3A and 3B, the solder mask 24 covers the substrate 12and the conductors 20. However, as shown in FIGS. 3C and 3D, the soldermask 24 includes openings 48 aligned with the wire bonding pads 40 andthe terminal contact bonding pads 44.

As shown in FIG. 3, the adjustment circuitry 19 also includes firstprogrammable links 50A proximate to the plating conductors 20P, andsecond programmable links 50B between the wire bonding pads 40 and theterminal contact bonding pads 44. As used herein the term “programmablelink” means an element that can be placed in either a first state(short) in which electrical current can be transmitted through the link,or in a second state (open) in which electrical current cannot betransmitted through the link.

Suitable programmable links include laser fuses, current fuses, laseranti-fuses, and current anti-fuses. A laser fuse includes a segment thatcan be broken by a laser beam to create an open circuit. A voltage fuseincludes a segment that can be broken by application of electricalcurrent having a sufficient amperage to create an open circuit. A laseranti-fuse includes conductive segments separated by a dielectric layerthat can be broken down by a laser beam to electrically connect theconductive segments to create a short circuit. A current anti fuse has adielectric layer that can be broken down by application of electricalcurrent having a sufficient amperage to create a short circuit.

In the embodiment illustrated in FIG. 3, the programmable links 50A, 50Bcomprise laser fuses which are initially fabricated in the first state(short), but which can be placed in the second state (open) byapplication of a laser beam. In FIG. 3 the programmable links 50A, 50Bin the first state (short) have a continuous line therethrough, whereasthe programmable links 50A, 50B in the second state (open) do not have aline therethrough.

As shown in FIG. 3E, the programmable links 50A, 50B can comprisebreakable segments 52 having a width W and a thickness T. The width Wand the thickness T can be selected such that a laser beam of apredetermined power will sever a breakable segment 52. The breakablesegments 52 can be formed of a same conductive material as theconductors 20, or can be formed of a different conductive material. Inaddition, the breakable segments 52 can be aligned with openings 48 inthe solder mask 24 to permit access by the laser beam.

The programmable links 50A function as “trimming links” for trimmingportions of the conductors 20. Specifically, in FIG. 3, the programmablelinks 50A have been placed in the second state (open) by application ofa laser beam. This removes or “trims” the plating conductors 20P fromthe conductors 20. For simplicity, the programmable links 50A areillustrated in rows proximate to the outer edges 54 of the substrate 12.However, each programmable link 50A can be located as close as possibleto a corresponding terminal contact bonding pad 44, such that as muchlength of the plating conductors 20P as is possible can be removed.Trimming of the plating conductors 20P improves the integrity of thesignals transmitted to and from the terminal contacts 28 (FIG. 2)because the superfluous conductive path through the plating conductors20P has been removed. In addition, the conductors 20 are more evenlymatched in length, such that their electrical characteristics and signaltransmitting capabilities are more evenly matched.

The programmable links 50B function as “input/output links” for changingthe input/output configuration of the terminal contacts 28.Specifically, in FIG. 3, some of the programmable links 50B have beenplaced in the second state (open) by application of a laser beam, whilesome of the programmable links 50B remain in the first state (short).The programmable links 50B allow selected conductors 20, and theirassociated terminal contact bonding pads 44, to be removed or “trimmed”from the input/output circuit of the component 10. The trimmedconductors are designated 20-T. As such, there is no conductive pathbetween a trimmed conductor 20-T and the die 30, and no conductive pathbetween the die 30 and the terminal contact 28 (FIG. 2) associated withthe trimmed conductor 20-T. This arrangement permits the input/outputconfiguration of the terminal contacts 28 (FIG. 2) to be changed andcustomized for a particular application. The electrical configuration ofthe component 10 can thus be customized as well.

In addition, this arrangement permits the wire bonding of the die 30 tothe conductors 20 to be standardized even for different types of dice.For example, a X4 die can be wire bonded in the same manner as a X16die, but with the unused terminal contacts 28 taken out of theinput/output circuit.

Referring to FIG. 4, a cross section equivalent to FIG. 3, of analternate embodiment component 10C is illustrated. The component 10C isconstructed substantially as previously described for component 10 (FIG.1), and includes essentially the same elements including adjustmentcircuitry 19C. However, in this embodiment the adjustment circuitry 19Calso includes capacitors 56 in electrical communication with theconductors 20 and the terminal contact bonding pads 44. In addition, theadjustment circuitry 19C includes programmable links 50C in electricalcommunication with the capacitors 56.

The programmable links 50C can comprise laser fuses, current fuses,laser anti-fuses or current anti-fuses, substantially as previouslydescribed for programmable links 50A, 50B in FIG. 3. The capacitors 56and programmable links 50C allow extra capacitance to be added or“trimmed” into the conductors 20. The capacitors 56 and programmablelinks SOC permit capacitance to be added to the conductive paths throughthe terminal contacts 28 (FIG. 1) such that the capacitance ofindividual terminal contacts 28, and the capacitance of selected groupsof the terminal contacts 28, can be adjusted and/or matched. Forexample, the terminal contacts 28 representing matching input/output pingroups for the component 10C can be matched.

In FIG. 4, the conductors having added capacitance are designated 20C.These conductors 20C are in electrical communication with a programmablelink 50C in the first state (short) such that electrical communicationwith a capacitor 56 is maintained. The other conductors 20 are inelectrical communication with a programmable link 50C in the secondstate (open) such that there is no electrical communication with acapacitor 56.

In the illustrative embodiment, the capacitors 56 and the programmablelinks 50C are located proximate to the terminal contact bonding pads 44,and are outside of the conductive paths between the terminal contactbonding pads 44 and the die 30. The capacitors 56 can compriseconductive plates separated by dielectric layers configured to provide adesired capacitance C. The capacitors 56 can be constructed usingtechniques that are known in the art, such as by deposition andpatterning of metal and dielectric layers. Alternately, the capacitors56 can comprise surface mount devices that are commercially availablefrom various manufacturers. The value of the capacitance C of eachcapacitor 56 can be selected as required, with from micro farads (μF) topico farads (pF) being representative. In addition to matching thecapacitance of the conductive paths for the terminal contacts 28, thecapacitors can also be used as by-pass filters for filtering transientvoltages, power supply noise and spurious signals.

Referring to FIG. 5, a cross sectional equivalent to FIG. 3, of analternate embodiment component 10I is illustrated. The component 10I isconstructed substantially as previously described for component 10 (FIG.1), and includes essentially the same elements including adjustmentcircuitry 19I. However, the adjustment circuitry 19I also includesinductance conductors 20I in electrical communication with theconductors 20, and with the terminal contact bonding pads 44. Inaddition, the inductance conductors 20I are in electrical communicationwith programmable links 50I. Each inductance conductor 20I andassociated programmable link 50I forms an adjustable conductive loopthat can be either by-passed, or added, depending on the state of theprogrammable link 50I.

The programmable links 50I can comprise laser fuses, current fuses,laser anti-fuses or current anti-fuses, substantially as previouslydescribed for programmable links 50A, 50B in FIG. 3. The inductanceconductors 20I and programmable links 50I allow extra inductance andresistance to be added or “trimmed” into the conductors 20

In FIG. 50, the inductance conductors 20I in electrical communicationwith the programmable links 50I in the second state (open) areactivated, whereas the inductance conductors 20I in electricalcommunication with the programmable links in the first state (short) arebypassed.

In FIG. 5, the inductance conductors 20I and programmable links 50I arelocated between the terminal contact bonding pads 44 and the wirebonding pads 40. In addition, each conductor 20 includes three separateinductance conductors 20I and programmable links 50I. However, thisarrangement is merely exemplary and other arrangements are possible.

Referring to FIGS. 6A-6F, steps in a method for fabricating thecomponent 10, 10C or 10I are illustrated. As shown in FIG. 6A, a panel58 containing multiple substrates 12 is initially provided. The panel 58is similar in function to a semiconductor leadframe, permitting thefabrication of multiple components 10, 10C or 10I at the same time.

As shown in FIG. 7A, the panel 58 includes circular indexing openings 62proximate to the longitudinal edges thereof. The indexing openings 62permit the panel 58 to be handled by automated transfer mechanismsassociated with chip bonders, wire bonders, molds, and trim machinery.In addition, the panel 58 includes elongated separation openings 60which facilitate singulation of the substrates 12 on the panel 58 intoseparate components 10, 10C or 10I. The panel 58 also includes a wirebonding opening 18 for each substrate 12. If desired, the panel 58 canbe constructed from a commercially produced bi-material core, such as acopper clad bismaleimide-triazine (BT) core, available from MitsubishiGas Chemical Corp., Japan. A representative weight of the copper can befrom 0.5 oz to 2 oz. per square foot.

Next, as shown in FIG. 6B, the adjustment circuitry 19 is formed on thesubstrate 12. As shown in FIG. 7B, the adjustment circuitry 19 includesthe conductors 20 and the programmable links 50A, 50B which are laid outsubstantially as previously described and shown in FIG. 3. In addition,the adjustment circuitry 19 includes the terminal contact bonding pads44, and the wire bonding pads 40 in electrical communication with theconductors 20.

The conductors 20 can comprise a highly conductive metal layer, which isblanket deposited onto the panel 58 (e.g., electroless or electrolyticplating), and then etched in required patterns. Alternately, an additiveprocess, such as electroless deposition through a mask, can be used.Suitable metals include copper, aluminum, titanium, tungsten, tantalum,platinum, molybdenum, cobalt, nickel, gold, and iridium.

The terminal contact bonding pads 44, and the wire bonding pads 40 canbe formed at the same time, and using the same process, as for theconductors 20. In addition, the non-oxidizing layers 46 (FIGS. 3C, 3D)can be formed on the terminal contact bonding pads 44, and the wirebonding pads 40 using a plating process, such as electrolyticdeposition. As shown in FIG. 7B, plating buses 64 can be used toelectrically connect the conductors 20 for performing the platingprocess. These plating buses 64 will be trimmed away during thesingulating step to be hereinafter described.

The programmable links 50A, 50B can be formed at the same time and usingthe same process as for the conductors 20. For example, the programmablelinks 50A, 50B can comprise segments of the conductors 20 formed byetching a blanket deposited layer using an etch mask, or by depositingmetal in a required pattern using a deposition mask. Alternately, theprogrammable links 50A, 50B can comprise surface mounted devices placedin electrical communication with the conductors 20.

Following formation of the adjustment circuitry 19 the solder mask 24(FIG. 3B), and the solder mask 26 (FIG. 2) can be formed. The soldermask 24 includes the openings 48 (FIGS. 3C and 3D) for the terminalcontact bonding pads 40, the wire bonding pads 44 and the programmablelinks 50A, 50B. The solder mask 26 includes a die sized opening on thedie attach area 22 (FIG. 2). The solder masks 24, 26 can comprise aphotoimageable dielectric material, such as a negative or positive toneresist. One suitable resist is commercially available from TaiyoAmerica, Inc., Carson City, Nev. under the trademark “PSR-4000”. The“PSR-4000” resist can be mixed with an epoxy such as epoxy “720”manufactured by Ciba-Geigy (e.g., 80% PSR-4000 and 20% epoxy “720”).Another suitable resist is commercially available from Shipley under thetrademark “XP-9500”.

Referring to FIG. 7C, the adjustment circuitry 19C can be configured aspreviously described and shown in FIG. 4, with capacitors 56 andprogrammable links 50C. The capacitors 56 can comprise etched ordeposited metal and dielectric layers formed substantially as previouslydescribed for the conductors 20. Alternately, the capacitors 56 cancomprise surface mounted devices placed in electrical communication withthe conductors 20. The programmable links 50C can be formedsubstantially as previously described for programmable links 50A, 50B.

Referring to FIG. 7D, the adjustment circuitry 19I can also beconfigured as previously described and shown in FIG. 5, with inductanceconductors 20I and programmable links 50I. The inductance conductors 20Ican comprise etched or deposited metal layers formed substantially aspreviously described for the conductors 20. The programmable links 50Ican be formed substantially as previously described for programmablelinks 50A, 50B.

Referring to FIG. 6C, following formation of the adjustment circuitry19, a laser beam 66 can be used to place selected programmable links50A, 50B (FIG. 7B), 50C (FIG. 7C) or 50I (FIG. 7D), in the open statesuch that no current can be transmitted therethrough. Suitable lasersystems for laser severing the breakable segments 52 (FIG. 3E) of theprogrammable links 50A, 50B are manufactured by Electro Scientific,Inc., of Portland, Oreg. as well as others.

Although the programmable links 50A, 50B, 50C, 50I are illustrated asbeing laser fuses, it is to be understood that these programmable linkscan also be configured as laser anti-fuses. In this case the laser beam66 would be used to place selected programmable links in the shortstate, such that current can be conducted therethrough.

Next, as shown in FIG. 6D, the die 30 can be attached to the substrate12 using conventional adhesives and die attach systems. In addition, thedie 30 can be wire bonded to the wire bonding pads 40 (FIG. 3) usingconventional wire bonding equipment.

Next, as shown in FIG. 6E, the die encapsulant 42 can be formed on thedie 30. The die encapsulant 42 can comprise a deposited or moldedpolymer. For example, the die encapsulant 42 can comprise a Novolacbased epoxy formed in a desired shape using a transfer molding process,and then cured using an oven. For simplicity, in FIG. 6E, the wire bondencapsulant 38 is not shown. However, the wire bond encapsulant 38 canbe formed using a suitable technique such as dispensing and curing aglob top polymer. As also shown in FIG. 6E, the terminal contacts 28 canbe formed on the terminal contact bonding pads 44 using a bondingprocess, such as solder reflow of pre-formed balls, or a depositionprocess such as electroless deposition of metal bumps.

Next, as shown in FIG. 6F, a singulation step can be performed tosingulate the components 10, 10C or 10I from the panel 58. Thesingulation step can be performed using a saw, a shear or anothersingulation apparatus. The singulation step also trims the plating buses64 (FIG. 7B) such that the conductors 20 are no longer electricallyconnected to one another.

Referring to FIGS. 8A-8B and 9A-9B, an alternate embodiment of thefabrication method illustrated in FIGS. 6A-6F is illustrated. As shownin FIG. 8A, an adjustment circuit 19S is formed on the substrate 12,substantially as previously described and shown in FIG. 6 for adjustmentcircuit 19. However, the adjustment circuit 19S includes programmablelinks 50S (FIG. 9A) configured as current fuses, or alternatelyprogrammable links 50AF configured as anti-fuses.

As shown in FIG. 9A, each programmable link 50S includes a necked downportion 72 (FIG. 9A) configured to blow, and form an open circuit uponapplication of a sufficient current. As shown in FIG. 9B, eachprogrammable link 50AF includes a pair of conductive plates 74A, 74Bseparated by a dielectric layer 76. Upon application of a sufficientcurrent, the dielectric layer 76 breaks down, such that electricalcommunication is established between the conductive plates 74A, 74B anda short circuit is formed. With the programmable link 50AF configured asan anti-fuse the same results can be achieved as with a fuse, providedthe state of the link (open or short) is opposite to that of the fuse.

As shown in FIG. 8B, a programming circuit 70 is configured to apply thecurrent signals necessary to place the programmable links 50S or 50AF inthe required state (i.e., open for programmable link 50S or short forprogrammable link 50AF). In addition, electrical connectors 68 such as“POGO PINS” establish electrical communication between the programmingcircuit 70 and the programmable links 50S or 50AF. The electricalconnectors can be constructed to electrically engage the terminalcontact bonding pads 44 (FIG. 3), the wire bonding pads 40 (FIG. 3) orother connection points on the adjustment circuit 19S.

Referring to FIGS. 10A and 10B, electronic systems constructed usingcomponents 10, 10C, 10I fabricated in accordance with the invention areillustrated. In general, the components 10, 10C, 10I can be used in anysystem in which semiconductor components as previously defined are used.

In FIG. 10A, a multi chip module system 80 includes a module substrate82 having an edge connector 84, and a plurality of conductors 86 inelectrical communication with the edge connector 84. The components 10,10C, 10I can be flip chip mounted to the module substrate 82, with theterminal contacts 28 (FIG. 1) thereon in electrical communication withthe conductors 86.

In FIG. 10B, a system in a package (SIP) 88 is constructed with one ormore components 10, 10C, 10I. This type of package is also referred toas a multi chip module MCM package. The system in a package (SIP) 88 canbe configured to perform a desired function such as micro processing.The system in a package (SIP) 88 includes a substrate 90 having terminalleads 92. The components 10, 10C, 10I can be flip chip mounted to thesubstrate 90, with the terminal contacts 28 thereon in electricalcommunication with the terminal leads 92. The system in a package (SIP)88 also includes a package body 94 encapsulating the components 110,10C, 10I and the substrate 90.

Thus the invention provides improved adjustable semiconductorcomponents, methods for fabricating the components, and systemsincorporating the component. While the invention has been described withreference to certain preferred embodiments, as will be apparent to thoseskilled in the art, certain changes and modifications can be madewithout departing from the scope of the invention as defined by thefollowing claims.

1. A method for fabricating a semiconductor component comprising:providing a substrate; forming an adjustment circuit on the substratecomprising a plurality of conductors, and a plurality of programmablelinks in electrical communication with the conductors; attaching a dieto the substrate in electrical communication with the conductors; andchanging a physical characteristic or an electrical characteristic of atleast one conductor by placing the programmable links in a selectedstate.
 2. The method of claim 1 wherein the physical characteristiccomprise length and the changing step trims the length.
 3. The method ofclaim 1 wherein the electrical characteristic comprises capacitance andthe changing step adds capacitance.
 4. The method of claim 1 wherein theelectrical characteristic comprises inductance and the changing stepadds inductance.
 5. The method of claim 1 further comprising formingterminal contacts on the substrate in electrical communication with theconductors and changing an input/output configuration of the terminalcontacts using the programmable links.
 6. A method for fabricating asemiconductor component comprising: providing a substrate; forming anadjustment circuit on the substrate comprising a plurality ofconductors, a plurality of programmable links in electricalcommunication with the conductors, and a plurality of capacitors inelectrical communication with the programmable links; attaching a die tothe substrate in electrical communication with the conductors; andadding capacitance to selected conductors by placing the programmablelinks in a selected state.
 7. The method of claim 6 further comprisingforming the adjustment circuit with a plurality of second programmablelinks configured to trim portions of the conductors, and trimming theportions using the second programmable links.
 8. The method of claim 6wherein the capacitors comprise metal and dielectric layers deposited onthe substrate.
 9. The method of claim 6 wherein the capacitors comprisesurface mounted devices.
 10. The method of claim 6 further comprisingchanging a physical characteristic of at least one conductor using atleast one programmable link.
 11. The method of claim 6 furthercomprising forming terminal contacts on the substrate in electricalcommunication with the conductors and changing an input/outputconfiguration of the terminal contacts using the programmable links. 12.A method for fabricating a semiconductor component comprising: providinga substrate; forming an adjustment circuit on the substrate comprising aplurality of conductors, a plurality of programmable links in electricalcommunication with the conductors, and a plurality of inductanceconductors in electrical communication with the programmable links;attaching a die to the substrate in electrical communication with theconductors; and adding inductance to selected conductors by placing theprogrammable links in a selected state.
 13. The method of claim 12further comprising forming the adjustment circuit with a plurality ofsecond programmable links configured to trim portions of the conductors,and trimming the portions using the second programmable links.
 14. Themethod of claim 12 wherein each conductor is associated with a pluralityof inductance conductors.
 15. The method of claim 12 further comprisingchanging a physical characteristic of at least one conductor using atleast one programmable link.
 16. The method of claim 12 furthercomprising forming terminal contacts on the substrate in electricalcommunication with the conductors and changing an input/outputconfiguration of the terminal contacts using the programmable links. 17.A method for fabricating a semiconductor component comprising: providinga substrate comprising a plurality of terminal contacts; attaching asemiconductor die to the substrate in electrical communication with theterminal contacts; providing an adjustment circuit on the substratecomprising a plurality of conductors and programmable links inelectrical communication with the die and the terminal contacts; andadjusting an electrical characteristic of at least one conductor and aninput/output configuration of the terminal contacts by placing at leastone of the programmable links in a selected state.
 18. The method ofclaim 17 wherein the electrical characteristic comprises capacitance andthe adjusting step adds capacitance.
 19. The method of claim 17 whereinthe electrical characteristic comprises inductance and the adjustingstep adds inductance.
 20. The method of claim 17 further comprisingchanging a physical characteristic of at least one conductor using atleast one programmable link.